IP PortfolioProcessorsriscv_vector
of_cpu_zve32_embedded_vector
Embedded vector extension unit
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Small vector unit implementing Zve32x or Zve32f for RV32 microcontrollers, sharing the scalar load/store path.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| vinsn | in | valid-qualified bus | 32 | |
| vresult | out | valid-qualified bus | 32 |
Standards
- RISC-V Vector 1.0 (Zve32x Zve32f)
More in riscv_vector
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rvv_unit | RISC-V vector unit | planned |
| of_cpu_rv64gcv_app | RV64GCV in-order core with integrated vector | planned |