IP PortfolioProcessorsriscv_vector
of_cpu_rv64gcv_app
RV64GCV in-order core with integrated vector
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
In-order RV64GC application core with a tightly integrated short-VLEN RVV 1.0 pipeline sharing the scalar issue stage, for Linux-class edge AI and media.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| debug_req | in | serial | 1 |
Standards
- RISC-V RV64GCV
- RISC-V Vector 1.0
- RISC-V Sv39
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_vector
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rvv_unit | RISC-V vector unit | planned |
| of_cpu_zve32_embedded_vector | Embedded vector extension unit | planned |