IP PortfolioProcessorsriscv_ooo
of_cpu_rva23_server
RVA23 server-class out-of-order core
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
Wide out-of-order core implementing the RVA23 profile including vector, hypervisor and cache management extensions, with large private L2 and coherent CHI port.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| debug_req | in | serial | 1 |
Standards
- RISC-V RVA23 Profile
- RISC-V Vector 1.0
- RISC-V Hypervisor 1.0
- AMBA CHI
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_ooo
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv64_ooo | RV64GC out-of-order core | planned |