IP PortfolioProcessorsriscv_rt
of_cpu_rv64_realtime
RV64 real-time core with MPU
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
RV64IMAC core without virtual memory, with PMP-based protection, TCMs and low interrupt latency for storage and network controllers needing 64-bit addressing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| debug_req | in | serial | 1 |
Standards
- RISC-V RV64IMAC
- RISC-V Privileged 1.12
- RISC-V Debug 0.13
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_rt
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv32_rt_clic | Real-time RV32 core with CLIC | planned |