of_cpu_ext_vector_crypto
Vector cryptography extension unit
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Vector lane functional units for Zvkned, Zvknh, Zvkg, Zvksed and Zvksh, attached to the RVV unit for bulk encryption and hashing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| op | in | valid-qualified bus | 512 | |
| res | out | valid-qualified bus | 256 |
Standards
- RISC-V Vector Cryptography 1.0
More in isa_ext
| ID | Block | Maturity |
|---|---|---|
| of_cpu_ext_bitmanip | Bit-manipulation extension unit | simulated |
| of_cpu_ext_scalar_crypto | Scalar cryptography extension unit | simulated |
| of_cpu_ext_packed_simd | Packed SIMD extension unit | planned |
| of_cpu_ext_matrix | Matrix extension unit | planned |
| of_cpu_ext_dot_product | Packed dot-product extension | planned |
| of_cpu_ext_dsp_hwloop | Hardware loop and addressing extension | planned |
| of_cpu_xif_adapter | CORE-V eXtension Interface adapter | planned |
| of_cpu_ext_cfi | Control-flow integrity extension unit | planned |