of_cpu_ext_matrix
Matrix extension unit
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Outer-product matrix unit with tile registers and integer and floating point multiply-accumulate, attached to a vector-capable core.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| op | in | valid-qualified bus | 256 | |
| res | out | valid-qualified bus | 256 |
Standards
No external standard applies.
Notes
RISC-V matrix extension task groups have not ratified a specification; the encoding follows the latest draft and is versioned.
More in isa_ext
| ID | Block | Maturity |
|---|---|---|
| of_cpu_ext_bitmanip | Bit-manipulation extension unit | simulated |
| of_cpu_ext_scalar_crypto | Scalar cryptography extension unit | simulated |
| of_cpu_ext_vector_crypto | Vector cryptography extension unit | planned |
| of_cpu_ext_packed_simd | Packed SIMD extension unit | planned |
| of_cpu_ext_dot_product | Packed dot-product extension | planned |
| of_cpu_ext_dsp_hwloop | Hardware loop and addressing extension | planned |
| of_cpu_xif_adapter | CORE-V eXtension Interface adapter | planned |
| of_cpu_ext_cfi | Control-flow integrity extension unit | planned |