of_cpu_ext_scalar_crypto
Scalar cryptography extension unit
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Execution unit for the scalar cryptography extensions (AES, SHA-2, SM3, SM4 round instructions and Zbkb/Zbkc/Zbkx) with data-independent timing.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| op | in | valid-qualified bus | 160 | |
| res | out | valid-qualified bus | 64 |
Standards
- RISC-V Scalar Cryptography 1.0.1 (Zkn Zks Zkt)
More in isa_ext
| ID | Block | Maturity |
|---|---|---|
| of_cpu_ext_bitmanip | Bit-manipulation extension unit | simulated |
| of_cpu_ext_vector_crypto | Vector cryptography extension unit | planned |
| of_cpu_ext_packed_simd | Packed SIMD extension unit | planned |
| of_cpu_ext_matrix | Matrix extension unit | planned |
| of_cpu_ext_dot_product | Packed dot-product extension | planned |
| of_cpu_ext_dsp_hwloop | Hardware loop and addressing extension | planned |
| of_cpu_xif_adapter | CORE-V eXtension Interface adapter | planned |
| of_cpu_ext_cfi | Control-flow integrity extension unit | planned |