of_cpu_ext_dot_product
Packed dot-product extension
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Custom extension for INT8 and INT4 packed dot products with accumulation for quantised neural network inference on microcontrollers.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| op | in | valid-qualified bus | 96 | |
| res | out | valid-qualified bus | 32 |
Standards
No external standard applies.
More in isa_ext
| ID | Block | Maturity |
|---|---|---|
| of_cpu_ext_bitmanip | Bit-manipulation extension unit | simulated |
| of_cpu_ext_scalar_crypto | Scalar cryptography extension unit | simulated |
| of_cpu_ext_vector_crypto | Vector cryptography extension unit | planned |
| of_cpu_ext_packed_simd | Packed SIMD extension unit | planned |
| of_cpu_ext_matrix | Matrix extension unit | planned |
| of_cpu_ext_dsp_hwloop | Hardware loop and addressing extension | planned |
| of_cpu_xif_adapter | CORE-V eXtension Interface adapter | planned |
| of_cpu_ext_cfi | Control-flow integrity extension unit | planned |