of_cpu_cross_trigger
Multicore cross-trigger matrix
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Event routing matrix that halts, resumes or signals trace start across harts and accelerators for synchronised multicore debug.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| trig_in | in | parallel | 16 | |
| trig_out | out | parallel | 16 |
Standards
No external standard applies.
More in debug
| ID | Block | Maturity |
|---|---|---|
| of_cpu_debug_module | RISC-V debug module | simulated |
| of_cpu_jtag_dtm | JTAG debug transport module | fpga-routed |
| of_cpu_trigger_module | Debug trigger module | planned |
| of_cpu_hpm_counters | Performance monitor counters | planned |
| of_cpu_ras_reri | RAS error record unit | planned |
| of_cpu_pc_profiler | PC sampling profiler | planned |