of_cpu_trace_etrace
E-Trace instruction trace encoder
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Branch-trace encoder that compresses the instruction trace interface of a hart into E-Trace packets.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| itrace | in | valid-qualified bus | 128 | |
| packets | out | AXI4-Stream | 32 |
Standards
- RISC-V Efficient Trace (E-Trace) 2.0
More in trace
| ID | Block | Maturity |
|---|---|---|
| of_cpu_trace_ntrace | N-Trace encoder | planned |
| of_cpu_trace_sink | Trace funnel and sink | planned |