of_cpu_trigger_module
Debug trigger module
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Hardware breakpoint and watchpoint triggers (mcontrol6, icount, itrigger, etrigger) with chaining and action selection.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- RISC-V Debug 1.0 (Sdtrig)
More in debug
| ID | Block | Maturity |
|---|---|---|
| of_cpu_debug_module | RISC-V debug module | simulated |
| of_cpu_jtag_dtm | JTAG debug transport module | fpga-routed |
| of_cpu_cross_trigger | Multicore cross-trigger matrix | planned |
| of_cpu_hpm_counters | Performance monitor counters | planned |
| of_cpu_ras_reri | RAS error record unit | planned |
| of_cpu_pc_profiler | PC sampling profiler | planned |