of_cpu_debug_module
RISC-V debug module
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Debug module with abstract register and memory commands, program buffer, system bus access, halt groups and multi-hart selection.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| dmi | in | valid-qualified bus | 41 | |
| halt_req | out | parallel | 8 |
Standards
- RISC-V Debug 0.13
- RISC-V Debug 1.0
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
Notes
OpenTitan rv_dm is the reference basis.
More in debug
| ID | Block | Maturity |
|---|---|---|
| of_cpu_jtag_dtm | JTAG debug transport module | fpga-routed |
| of_cpu_trigger_module | Debug trigger module | planned |
| of_cpu_cross_trigger | Multicore cross-trigger matrix | planned |
| of_cpu_hpm_counters | Performance monitor counters | planned |
| of_cpu_ras_reri | RAS error record unit | planned |
| of_cpu_pc_profiler | PC sampling profiler | planned |