IP PortfolioInterface controllerstsn
of_tsn_switch
TSN Ethernet switch
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Multi-port 1G/10G Ethernet switch with VLAN bridging, 802.1Qbv/Qav shaping, 802.1Qci per-stream policing, gPTP relay and cut-through option.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| port_rx | in | AXI4-Stream | 256 | |
| port_tx | out | AXI4-Stream | 256 |
Standards
- IEEE 802.1Q-2022
- IEEE 802.1AS-2020
- IEEE 802.1Qci-2017
More in tsn
| ID | Block | Maturity |
|---|---|---|
| of_tsn_gptp | gPTP time synchronisation unit | simulated |
| of_tsn_qbv | Time-aware shaper (802.1Qbv) | planned |
| of_tsn_qbu | Frame preemption (802.1Qbu/802.3br) | planned |
| of_tsn_frer | Frame replication and elimination (802.1CB) | planned |