IP PortfolioInterface controllerstsn
of_tsn_gptp
gPTP time synchronisation unit
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
IEEE 802.1AS time-aware system support with per-port ingress/egress timestamping, adjustable PTP hardware clock, PPS output and event capture.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pps_out | out | serial | 1 | |
| evt_in | in | parallel | 4 | |
| ts | out | valid-qualified bus | 96 |
Standards
- IEEE 802.1AS-2020
- IEEE 1588-2019
Basis projects
Permissive open projects the implementation may build on.
- verilog-ethernet (MIT)
More in tsn
| ID | Block | Maturity |
|---|---|---|
| of_tsn_qbv | Time-aware shaper (802.1Qbv) | planned |
| of_tsn_qbu | Frame preemption (802.1Qbu/802.3br) | planned |
| of_tsn_frer | Frame replication and elimination (802.1CB) | planned |
| of_tsn_switch | TSN Ethernet switch | planned |