IP PortfolioInterface controllerstsn
of_tsn_frer
Frame replication and elimination (802.1CB)
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
802.1CB stream identification, sequence generation, replication across redundant paths and vector or match recovery for seamless redundancy.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| rx | in | AXI4-Stream | 64 | |
| tx | out | AXI4-Stream | 64 |
Standards
- IEEE 802.1CB-2017
More in tsn
| ID | Block | Maturity |
|---|---|---|
| of_tsn_gptp | gPTP time synchronisation unit | simulated |
| of_tsn_qbv | Time-aware shaper (802.1Qbv) | planned |
| of_tsn_qbu | Frame preemption (802.1Qbu/802.3br) | planned |
| of_tsn_switch | TSN Ethernet switch | planned |