IP PortfolioInterface controllersdram
of_ddr3_ctrl
DDR3/DDR3L memory controller
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
DDR3 and DDR3L SDRAM controller with bank-aware scheduler, open-page policy, refresh and ZQ calibration management, AXI4 host port and DFI 3.1 PHY interface.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| host | in | AXI4-Stream | 128 | |
| dfi | out | parallel | 256 | |
| dfi_rd | in | valid-qualified bus | 128 |
Standards
- JEDEC JESD79-3
- DFI 3.1
Basis projects
Permissive open projects the implementation may build on.
- LiteDRAM (BSD-2-Clause)
More in dram
| ID | Block | Maturity |
|---|---|---|
| of_ddr4_ctrl | DDR4 memory controller | planned |
| of_ddr5_ctrl | DDR5 memory controller | planned |
| of_ddr5_mrdimm_ctrl | DDR5 MRDIMM host controller | planned |
| of_lpddr4_ctrl | LPDDR4/LPDDR4X memory controller | planned |
| of_lpddr5_ctrl | LPDDR5/LPDDR5X memory controller | planned |
| of_lpddr6_ctrl | LPDDR6 memory controller | planned |
| of_gddr6_ctrl | GDDR6 memory controller | planned |
| of_gddr7_ctrl | GDDR7 memory controller | planned |