IP PortfolioInterface controllersfieldbus
of_encoder_ssi_biss
SSI and BiSS-C encoder master
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 3
Absolute position encoder master for SSI and BiSS-C with line delay compensation, CRC checking and register or sensor data channels.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| ma | out | clock | 1 | |
| slo | in | serial | 1 |
Standards
No external standard applies.
More in fieldbus
| ID | Block | Maturity |
|---|---|---|
| of_modbus_rtu | Modbus RTU/ASCII framer | planned |
| of_iolink_master | IO-Link master port | planned |
| of_iolink_device | IO-Link device | planned |
| of_dali | DALI-2 lighting control interface | planned |