IP PortfolioVerification IPethernet vip
of_vip_eth_xgmii_mon
Ethernet XGMII/XLGMII/CGMII monitor and protocol checker
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
10G to 400G MAC-PCS interface monitor decoding control characters, start/terminate alignment, ordered sets, link fault signaling and frame FCS.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 72 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- IEEE 802.3
Basis projects
Permissive open projects the implementation may build on.
- cocotbext-eth (MIT)
More in ethernet vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_eth_mii_mon | Ethernet MII/RMII/GMII/RGMII monitor and protocol checker | simulated |
| of_vip_eth_mii_bfm | Ethernet MII/RMII/GMII/RGMII bus functional model and agent | simulated |
| of_vip_eth_xgmii_bfm | Ethernet XGMII/XLGMII/CGMII bus functional model and agent | planned |
| of_vip_eth_pkt_gen | Ethernet packet generator and checker | planned |