IP PortfolioVerification IPethernet vip
of_vip_eth_xgmii_bfm
Ethernet XGMII/XLGMII/CGMII bus functional model and agent
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
XGMII-family source and sink agents with idle insertion and deletion, fault sequences and frame generation at configurable lane widths.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| txd | out | parallel | 64 | |
| txc | out | parallel | 8 | |
| rxd | in | parallel | 64 | |
| rxc | in | parallel | 8 |
Standards
- IEEE 802.3
Basis projects
Permissive open projects the implementation may build on.
- cocotbext-eth (MIT)
More in ethernet vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_eth_mii_mon | Ethernet MII/RMII/GMII/RGMII monitor and protocol checker | simulated |
| of_vip_eth_mii_bfm | Ethernet MII/RMII/GMII/RGMII bus functional model and agent | simulated |
| of_vip_eth_xgmii_mon | Ethernet XGMII/XLGMII/CGMII monitor and protocol checker | planned |
| of_vip_eth_pkt_gen | Ethernet packet generator and checker | planned |