IP PortfolioVerification IPethernet vip
of_vip_eth_mii_bfm
Ethernet MII/RMII/GMII/RGMII bus functional model and agent
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Ethernet PHY-side and MAC-side agents generating and receiving frames with VLAN tags, pause frames, runt and error frames on MII-family interfaces.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| txd | out | parallel | 8 | |
| rxd | in | parallel | 8 | |
| tx_ctl | out | parallel | 2 | |
| rx_ctl | in | parallel | 2 |
Standards
- IEEE 802.3
Basis projects
Permissive open projects the implementation may build on.
- cocotbext-eth (MIT)
More in ethernet vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_eth_mii_mon | Ethernet MII/RMII/GMII/RGMII monitor and protocol checker | simulated |
| of_vip_eth_xgmii_mon | Ethernet XGMII/XLGMII/CGMII monitor and protocol checker | planned |
| of_vip_eth_xgmii_bfm | Ethernet XGMII/XLGMII/CGMII bus functional model and agent | planned |
| of_vip_eth_pkt_gen | Ethernet packet generator and checker | planned |