IP PortfolioSoC interconnectwishbone, tilelink and obi
of_wb_xbar
Wishbone B4 pipelined crossbar
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
N x M Wishbone B4 pipelined-mode crossbar with per-slave round-robin arbitration, address decoding and STALL handling, allowing concurrent transfers.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_wb | in | valid-qualified bus | 72 | |
| m_wb | out | valid-qualified bus | 72 |
Standards
- Wishbone B4
Basis projects
Permissive open projects the implementation may build on.
- verilog-wishbone (MIT)
More in wishbone, tilelink and obi
| ID | Block | Maturity |
|---|---|---|
| of_wb_ic | Wishbone B4 shared-bus interconnect | simulated |
| of_wb_axil_bridge | Wishbone and AXI4-Lite bridges | planned |
| of_tlul_xbar | TileLink TL-UL crossbar | planned |
| of_tl_axi4_bridge | TileLink to AXI4 bridge | planned |
| of_obi_xbar | OBI crossbar and AXI4 bridge | planned |