IP PortfolioSoC interconnectwishbone, tilelink and obi
of_tl_axi4_bridge
TileLink to AXI4 bridge
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Converts TileLink TL-UL and TL-UH (bursts, atomics) requests into AXI4 transactions and AXI4 responses back into TileLink D-channel messages.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_tl | in | valid-qualified bus | 108 | |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
- SiFive TileLink 1.8
- AMBA AXI4
More in wishbone, tilelink and obi
| ID | Block | Maturity |
|---|---|---|
| of_wb_ic | Wishbone B4 shared-bus interconnect | simulated |
| of_wb_xbar | Wishbone B4 pipelined crossbar | planned |
| of_wb_axil_bridge | Wishbone and AXI4-Lite bridges | planned |
| of_tlul_xbar | TileLink TL-UL crossbar | planned |
| of_obi_xbar | OBI crossbar and AXI4 bridge | planned |