IP PortfolioSoC interconnectwishbone, tilelink and obi
of_tlul_xbar
TileLink TL-UL crossbar
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
TileLink Uncached Lightweight crossbar with address decoding, per-device arbitration, asynchronous FIFOs for clock crossings and an error responder.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_tl | in | valid-qualified bus | 108 | |
| m_tl | out | valid-qualified bus | 108 |
Standards
- SiFive TileLink 1.8
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in wishbone, tilelink and obi
| ID | Block | Maturity |
|---|---|---|
| of_wb_ic | Wishbone B4 shared-bus interconnect | simulated |
| of_wb_xbar | Wishbone B4 pipelined crossbar | planned |
| of_wb_axil_bridge | Wishbone and AXI4-Lite bridges | planned |
| of_tl_axi4_bridge | TileLink to AXI4 bridge | planned |
| of_obi_xbar | OBI crossbar and AXI4 bridge | planned |