Register bank core (register-map driven)

Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1

Protocol-independent bank of up to 16 32-bit registers whose types (RW, RO, W1C, W1P), reset values and writable-bit masks come from a register-map specification passed as packed parameters (generated by openforge.iplib.regmap). Shared core of of_apb_regs, of_axil_regs and of_wb_regs.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
hw_in	in	parallel	32
hw_out	out	parallel	32

Standards

No external standard applies.

More in register blocks

ID	Block	Maturity
of_apb_regs	APB slave register block	fpga-routed
of_axil_regs	AXI4-Lite slave register block	simulated
of_wb_regs	Wishbone B4 slave register block	simulated