IP PortfolioSoC interconnectmemory system and caches
of_tcm_ctrl
Tightly coupled memory controller
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Single-cycle instruction and data TCM controller with a DMA access port, arbitration between core and DMA, and optional ECC.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| core_port | in | valid-qualified bus | 72 | |
| dma_port | in | valid-qualified bus | 72 |
Standards
No external standard applies.
More in memory system and caches
| ID | Block | Maturity |
|---|---|---|
| of_l2_cache | Shared L2 cache controller | planned |
| of_llc_dir | Last-level cache with coherence directory | planned |
| of_ecc_scrubber | Memory ECC scrubber | planned |