IP PortfolioSoC interconnectmemory system and caches
of_llc_dir
Last-level cache with coherence directory
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
Banked inclusive last-level cache with an integrated directory or snoop filter tracking sharers for MESI/MOESI coherence among several L1/L2 agents.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| req_ports | in | valid-qualified bus | 512 | |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
No external standard applies.
More in memory system and caches
| ID | Block | Maturity |
|---|---|---|
| of_l2_cache | Shared L2 cache controller | planned |
| of_ecc_scrubber | Memory ECC scrubber | planned |
| of_tcm_ctrl | Tightly coupled memory controller | planned |