IP PortfolioSoC interconnectmemory system and caches
of_l2_cache
Shared L2 cache controller
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Set-associative write-back L2 cache with configurable size, ways and line length, MSHRs for non-blocking misses, ECC on tags and data, and maintenance operations.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| s_axi | in | valid-qualified bus | 256 | AXI4 slave port (AW/W/AR channels) |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
- AMBA AXI4
More in memory system and caches
| ID | Block | Maturity |
|---|---|---|
| of_llc_dir | Last-level cache with coherence directory | planned |
| of_ecc_scrubber | Memory ECC scrubber | planned |
| of_tcm_ctrl | Tightly coupled memory controller | planned |