RISC-V PLIC

Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1

Platform-level interrupt controller with up to 1023 sources, per-source priority, per-context enables and thresholds, claim/complete and level or edge gateways.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
src	in	parallel	64
eip	out	parallel	8

Standards

RISC-V Platform-Level Interrupt Controller Specification 1.0.0

Basis projects

Permissive open projects the implementation may build on.

OpenTitan (Apache-2.0)

More in interrupt controllers

ID	Block	Maturity
of_irq_agg	Interrupt aggregator	simulated
of_clic	RISC-V CLIC	planned
of_aplic	RISC-V APLIC	planned
of_imsic	RISC-V IMSIC	planned
of_gic_style	GIC-style interrupt distributor	planned