IP PortfolioSoC interconnectinterrupt controllers
of_gic_style
GIC-style interrupt distributor
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Interrupt distributor and per-core interface with shared, private and software-generated interrupts, group and priority masking, and affinity routing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| spi_src | in | parallel | 128 | |
| core_irq | out | parallel | 8 |
Standards
No external standard applies.
Notes
GIC-style register model; not an implementation of a licensed Arm architecture.
More in interrupt controllers
| ID | Block | Maturity |
|---|---|---|
| of_irq_agg | Interrupt aggregator | simulated |
| of_plic | RISC-V PLIC | simulated |
| of_clic | RISC-V CLIC | planned |
| of_aplic | RISC-V APLIC | planned |
| of_imsic | RISC-V IMSIC | planned |