RISC-V APLIC

Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2

Advanced platform-level interrupt controller with interrupt domains, source modes, delegation and direct delivery or forwarding as MSIs to IMSICs.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
src	in	parallel	64
eip	out	parallel	8
m_msi	out	valid-qualified bus	64

Standards

RISC-V Advanced Interrupt Architecture 1.0

More in interrupt controllers

ID	Block	Maturity
of_irq_agg	Interrupt aggregator	simulated
of_plic	RISC-V PLIC	simulated
of_clic	RISC-V CLIC	planned
of_imsic	RISC-V IMSIC	planned
of_gic_style	GIC-style interrupt distributor	planned