IP PortfolioSecurityattestation
of_sec_dice
DICE identity engine
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Hardware implementation of DICE layering: measures the next firmware layer, derives the compound device identifier and erases parent secrets.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
- TCG DICE
- TCG DICE Attestation Architecture
More in attestation
| ID | Block | Maturity |
|---|---|---|
| of_sec_spdm | SPDM responder engine | planned |