IP PortfolioSecurityinline_crypto
of_sec_crypto_dma
Descriptor-based crypto offload engine
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Multi-channel DMA front end that chains cipher, hash and AEAD operations described by descriptors and dispatches them to crypto cores.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
- AMBA AXI4
More in inline_crypto
| ID | Block | Maturity |
|---|---|---|
| of_sec_wlan_ccmp_gcmp | WLAN CCMP and GCMP inline engine | planned |
| of_sec_macsec | MACsec engine | planned |
| of_sec_ipsec | IPsec ESP engine | planned |
| of_sec_tls_record | TLS record offload | planned |
| of_sec_pcie_ide | PCIe IDE engine | planned |
| of_sec_cxl_ide | CXL IDE engine | planned |
| of_sec_storage_inline | Inline storage crypto engine | planned |
| of_sec_sed_band_mgr | Self-encrypting drive band manager | planned |