of_sec_aes_xts
AES-XTS storage encryption engine
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
XTS-AES-128/256 engine with tweak generation per data unit and ciphertext stealing for block storage encryption.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| data_in | in | AXI4-Stream | 256 | |
| data_out | out | AXI4-Stream | 256 |
Standards
- NIST FIPS 197
- IEEE 1619-2018
- NIST SP 800-38E
More in aes
| ID | Block | Maturity |
|---|---|---|
| of_sec_aes_core | AES block cipher core | simulated |
| of_sec_aes_modes | AES modes engine | simulated |
| of_sec_aes_gcm | AES-GCM authenticated encryption engine | planned |
| of_sec_aes_masked | Side-channel protected AES | planned |
| of_sec_aes_keywrap | AES key wrap engine | planned |
| of_sec_aes_gcm_siv | AES-GCM-SIV engine | planned |