of_sec_aes_masked
Side-channel protected AES
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
AES core with first-order domain-oriented masking, fresh randomness from an entropy interface and fault detection by redundancy.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| blk_in | in | AXI4-Stream | 128 | |
| blk_out | out | AXI4-Stream | 128 | |
| rnd_in | in | valid-qualified bus | 64 |
Standards
- NIST FIPS 197
- ISO/IEC 17825
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in aes
| ID | Block | Maturity |
|---|---|---|
| of_sec_aes_core | AES block cipher core | simulated |
| of_sec_aes_modes | AES modes engine | simulated |
| of_sec_aes_gcm | AES-GCM authenticated encryption engine | planned |
| of_sec_aes_xts | AES-XTS storage encryption engine | simulated |
| of_sec_aes_keywrap | AES key wrap engine | planned |
| of_sec_aes_gcm_siv | AES-GCM-SIV engine | planned |