of_sec_aes_core
AES block cipher core
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Iterative AES-128/192/256 encrypt and decrypt core with on-the-fly key expansion and a key sideload port.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| blk_in | in | AXI4-Stream | 128 | |
| blk_out | out | AXI4-Stream | 128 | |
| key_in | in | valid-qualified bus | 256 |
Standards
- NIST FIPS 197
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in aes
| ID | Block | Maturity |
|---|---|---|
| of_sec_aes_modes | AES modes engine | simulated |
| of_sec_aes_gcm | AES-GCM authenticated encryption engine | planned |
| of_sec_aes_xts | AES-XTS storage encryption engine | simulated |
| of_sec_aes_masked | Side-channel protected AES | planned |
| of_sec_aes_keywrap | AES key wrap engine | planned |
| of_sec_aes_gcm_siv | AES-GCM-SIV engine | planned |