IP PortfolioQuantum controlqec
of_q_qec_window
Sliding-window decoding coordinator
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Splits the syndrome stream into overlapping time windows, dispatches them to parallel decoders and stitches committed corrections.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| syn_in | in | AXI4-Stream | 256 | |
| win_out | out | AXI4-Stream | 256 |
Standards
No external standard applies.
More in qec
| ID | Block | Maturity |
|---|---|---|
| of_q_qec_uf | Union-find surface code decoder | planned |
| of_q_qec_mwpm | Minimum-weight perfect matching accelerator | planned |
| of_q_qec_lut | Lookup-table decoder | planned |
| of_q_qec_nn | Neural network decoder engine | planned |
| of_q_qec_bp_osd | Belief propagation decoder for qLDPC codes | planned |
| of_q_syndrome_sched | Syndrome extraction scheduler | simulated |
| of_q_syndrome_net | Syndrome aggregation network | simulated |
| of_q_lattice_surgery | Lattice surgery scheduler | planned |
| of_q_pauli_frame | Pauli frame tracker | simulated |
| of_q_feedback_ctrl | Real-time feedback controller | planned |