IP PortfolioQuantum controlqec
of_q_pauli_frame
Pauli frame tracker
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Tracks accumulated Pauli corrections per qubit and applies them to measurement results and conditional gates without physical correction pulses.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| corr_in | in | AXI4-Stream | 256 | |
| meas_in | in | valid-qualified bus | 64 | |
| meas_out | out | valid-qualified bus | 64 |
Standards
No external standard applies.
More in qec
| ID | Block | Maturity |
|---|---|---|
| of_q_qec_uf | Union-find surface code decoder | planned |
| of_q_qec_mwpm | Minimum-weight perfect matching accelerator | planned |
| of_q_qec_lut | Lookup-table decoder | planned |
| of_q_qec_nn | Neural network decoder engine | planned |
| of_q_qec_bp_osd | Belief propagation decoder for qLDPC codes | planned |
| of_q_qec_window | Sliding-window decoding coordinator | planned |
| of_q_syndrome_sched | Syndrome extraction scheduler | simulated |
| of_q_syndrome_net | Syndrome aggregation network | simulated |
| of_q_lattice_surgery | Lattice surgery scheduler | planned |
| of_q_feedback_ctrl | Real-time feedback controller | planned |