of_cpu_trace_sink
Trace funnel and sink
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Trace funnel merging multiple encoders, with an on-chip RAM sink, system memory sink and a parallel trace port for external probes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| trace_in | in | AXI4-Stream | 32 | |
| trace_port | out | parallel | 16 |
Standards
No external standard applies.
More in trace
| ID | Block | Maturity |
|---|---|---|
| of_cpu_trace_etrace | E-Trace instruction trace encoder | planned |
| of_cpu_trace_ntrace | N-Trace encoder | planned |