IP PortfolioProcessorsriscv_mcu
of_cpu_rv32imac_zc_mcu
RV32IMAC core with Zb and Zc
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Three-stage RV32IMAC core adding the bit-manipulation and code-size reduction extensions for dense firmware on flash-limited microcontrollers.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| debug_req | in | serial | 1 |
Standards
- RISC-V RV32IMAC
- RISC-V Bitmanip 1.0 (Zba Zbb Zbc Zbs)
- RISC-V Zc 1.0
- RISC-V Debug 0.13
Basis projects
Permissive open projects the implementation may build on.
- Hazard3 (Apache-2.0)
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_mcu
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv32e_tiny | RV32E minimal core | simulated |
| of_cpu_rv32_bitserial | Bit-serial RV32I core | planned |
| of_cpu_rv32imc_mcu | RV32IMC microcontroller core | simulated |
| of_cpu_rv32imfc_perf | RV32IMFC performance MCU core | simulated |
| of_cpu_rv32_dual_issue | Dual-issue in-order RV32 core | planned |