IP PortfolioProcessorsriscv_mcu
of_cpu_rv32_dual_issue
Dual-issue in-order RV32 core
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Six-stage dual-issue in-order RV32IMAFDC core with branch prediction, instruction and data caches plus tightly coupled memories for high-end microcontrollers.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| debug_req | in | serial | 1 |
Standards
- RISC-V RV32IMAFDC
- IEEE 754-2019
- RISC-V Debug 0.13
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_mcu
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv32e_tiny | RV32E minimal core | simulated |
| of_cpu_rv32_bitserial | Bit-serial RV32I core | planned |
| of_cpu_rv32imc_mcu | RV32IMC microcontroller core | simulated |
| of_cpu_rv32imac_zc_mcu | RV32IMAC core with Zb and Zc | planned |
| of_cpu_rv32imfc_perf | RV32IMFC performance MCU core | simulated |