IP PortfolioProcessorsriscv_mcu
of_cpu_rv32_bitserial
Bit-serial RV32I core
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Bit-serial RV32I/RV32E core that processes one bit per cycle to minimise area, for deeply embedded control where throughput is irrelevant.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| timer_irq | in | serial | 1 |
Standards
- RISC-V RV32I
- RISC-V RV32E
Basis projects
Permissive open projects the implementation may build on.
- SERV (ISC)
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_mcu
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv32e_tiny | RV32E minimal core | simulated |
| of_cpu_rv32imc_mcu | RV32IMC microcontroller core | simulated |
| of_cpu_rv32imac_zc_mcu | RV32IMAC core with Zb and Zc | planned |
| of_cpu_rv32imfc_perf | RV32IMFC performance MCU core | simulated |
| of_cpu_rv32_dual_issue | Dual-issue in-order RV32 core | planned |