of_cpu_mmu
MMU with TLBs and page table walker
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Configurable MMU with split L1 TLBs, shared L2 TLB and hardware page table walker for Sv39, Sv48 and Sv57 including Svnapot and Svpbmt.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| vreq | in | valid-qualified bus | 64 | |
| preq | out | valid-qualified bus | 64 |
Standards
- RISC-V Privileged 1.12
- RISC-V Sv39
- RISC-V Sv48
- RISC-V Sv57
- RISC-V Svnapot
- RISC-V Svpbmt
More in mmu
| ID | Block | Maturity |
|---|---|---|
| of_cpu_pmp_unit | PMP and ePMP checker | simulated |