of_cpu_fpu_compact
Area-optimised iterative FPU
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Small single-precision FPU with an iterative multiplier and divider, optionally using the integer register file (Zfinx), for low-cost microcontrollers.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| op | in | valid-qualified bus | 100 | |
| res | out | valid-qualified bus | 32 |
Standards
- IEEE 754-2019
- RISC-V F
- RISC-V Zfinx
More in fpu
| ID | Block | Maturity |
|---|---|---|
| of_cpu_fpu_multiformat | Multi-format pipelined FPU | simulated |