IP PortfolioProcessorshypervisor
of_cpu_hypervisor_ext
Hypervisor extension unit
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Add-on for RV64 cores implementing the H extension: VS/VU modes, two-stage address translation (Sv39x4/Sv48x4) and virtual interrupt state.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- RISC-V Hypervisor 1.0