IP PortfolioProcessorsmcu_subsystem
of_cpu_microsequencer
Programmable microsequencer
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 3
Minimal custom-ISA sequencer with a small instruction RAM for power, test and peripheral sequencing where a full core is unnecessary.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| ctrl_out | out | parallel | 32 | |
| status_in | in | parallel | 32 |
Standards
No external standard applies.
More in mcu_subsystem
| ID | Block | Maturity |
|---|---|---|
| of_cpu_mcu_subsys_basic | Basic RV32 microcontroller subsystem | simulated |
| of_cpu_mcu_subsys_lowpower | Low-power IoT MCU subsystem | planned |
| of_cpu_mcu_subsys_auto | Automotive MCU subsystem | planned |
| of_cpu_soc_mgmt | SoC management controller | simulated |
| of_cpu_power_ctrl | Core power and clock controller | planned |
| of_cpu_hw_rtos | Hardware RTOS scheduler | planned |
| of_cpu_pio | Programmable I/O state machines | planned |
| of_cpu_amo_unit | Far atomic memory operation unit | planned |
| of_cpu_boot_ctrl | Multi-source boot controller | planned |