of_cpu_mcs51_compat
MCS-51 compatible 8-bit core
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
Pipelined 8-bit core executing the MCS-51 instruction set for reuse of legacy 8051 firmware in mixed-signal and industrial chips.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_int | in | parallel | 8 | |
| port_io | inout | parallel | 32 |
Standards
No external standard applies.