IP PortfolioProcessorsmcu_subsystem
of_cpu_soc_mgmt
SoC management controller
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Small RV32 controller for power-up sequencing, clock and reset configuration, fuse loading and telemetry of a larger SoC.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pwr_good | in | parallel | 16 | |
| rst_out | out | parallel | 16 |
Standards
No external standard applies.
More in mcu_subsystem
| ID | Block | Maturity |
|---|---|---|
| of_cpu_mcu_subsys_basic | Basic RV32 microcontroller subsystem | simulated |
| of_cpu_mcu_subsys_lowpower | Low-power IoT MCU subsystem | planned |
| of_cpu_mcu_subsys_auto | Automotive MCU subsystem | planned |
| of_cpu_power_ctrl | Core power and clock controller | planned |
| of_cpu_hw_rtos | Hardware RTOS scheduler | planned |
| of_cpu_pio | Programmable I/O state machines | planned |
| of_cpu_microsequencer | Programmable microsequencer | planned |
| of_cpu_amo_unit | Far atomic memory operation unit | planned |
| of_cpu_boot_ctrl | Multi-source boot controller | planned |