of_cpu_l1i_cache
L1 instruction cache
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Set-associative instruction cache with configurable size, line and ways, parity or ECC, next-line prefetch and Zifencei invalidation.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| fetch | in | valid-qualified bus | 64 | |
| insn | out | valid-qualified bus | 128 |
Standards
- RISC-V Zifencei
More in cache
| ID | Block | Maturity |
|---|---|---|
| of_cpu_l1d_cache | L1 data cache | planned |
| of_cpu_l2_cache | Shared L2 cache | planned |
| of_cpu_llc_partitioned | Last-level cache slice with QoS | planned |
| of_cpu_prefetcher | Hardware data prefetcher | planned |
| of_cpu_tcm_ctrl | Tightly coupled memory controller | simulated |
| of_cpu_xip_cache | Execute-in-place flash cache | planned |