of_cpu_prefetcher
Hardware data prefetcher
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Stride and stream prefetcher with confidence tracking that issues prefetches into L1 or L2 based on observed miss addresses.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| miss | in | valid-qualified bus | 64 | |
| pf_req | out | valid-qualified bus | 64 |
Standards
- RISC-V Zicbop
More in cache
| ID | Block | Maturity |
|---|---|---|
| of_cpu_l1i_cache | L1 instruction cache | simulated |
| of_cpu_l1d_cache | L1 data cache | planned |
| of_cpu_l2_cache | Shared L2 cache | planned |
| of_cpu_llc_partitioned | Last-level cache slice with QoS | planned |
| of_cpu_tcm_ctrl | Tightly coupled memory controller | simulated |
| of_cpu_xip_cache | Execute-in-place flash cache | planned |