IP PortfolioProcessorsbranch_pred
of_cpu_bp_tage
TAGE-class branch predictor
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Tagged geometric-history predictor with statistical corrector, loop predictor and indirect target prediction for wide out-of-order front ends.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| fetch_pc | in | valid-qualified bus | 64 | |
| pred | out | valid-qualified bus | 130 | |
| update | in | valid-qualified bus | 200 |
Standards
No external standard applies.
More in branch_pred
| ID | Block | Maturity |
|---|---|---|
| of_cpu_bp_gshare | Branch predictor for in-order cores | simulated |